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Sheet目录3881

308页 309页 310页 311页 [312页]313页 314页 315页 316页

PIC18F6585/8585/6680/8680

DS30491C-page 36

2004 Microchip Technology Inc.

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS

Register

Applicable Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

RESET

Instruction

Stack Resets

Wake-up via WDT

or Interrupt

TOSU

PIC18F6X8X PIC18F8X8X

---0 0000

---0 uuuu(3)

TOSH

PIC18F6X8X PIC18F8X8X

0000 0000

uuuu uuuu(3)

TOSL

PIC18F6X8X PIC18F8X8X

0000 0000

uuuu uuuu(3)

STKPTR

PIC18F6X8X PIC18F8X8X

00-0 0000

uu-0 0000

uu-u uuuu(3)

PCLATU

PIC18F6X8X PIC18F8X8X

---0 0000

---u uuuu

PCLATH

PIC18F6X8X PIC18F8X8X

0000 0000

uuuu uuuu

PCL

PIC18F6X8X PIC18F8X8X

0000 0000

PC + 2(2)

TBLPTRU

PIC18F6X8X PIC18F8X8X

--00 0000

--uu uuuu

TBLPTRH

PIC18F6X8X PIC18F8X8X

0000 0000

uuuu uuuu

TBLPTRL

PIC18F6X8X PIC18F8X8X

0000 0000

uuuu uuuu

TABLAT

PIC18F6X8X PIC18F8X8X

0000 0000

uuuu uuuu

PRODH

PIC18F6X8X PIC18F8X8X

xxxx xxxx

uuuu uuuu

PRODL

PIC18F6X8X PIC18F8X8X

xxxx xxxx

uuuu uuuu

INTCON

PIC18F6X8X PIC18F8X8X

0000 000x

uuuu uuuu(1)

INTCON2

PIC18F6X8X PIC18F8X8X

1111 1111

uuuu uuuu(1)

INTCON3

PIC18F6X8X PIC18F8X8X

1100 0000

uuuu uuuu(1)

INDF0

PIC18F6X8X PIC18F8X8X

N/A

POSTINC0

PIC18F6X8X PIC18F8X8X

N/A

POSTDEC0

PIC18F6X8X PIC18F8X8X

N/A

PREINC0

PIC18F6X8X PIC18F8X8X

N/A

PLUSW0

PIC18F6X8X PIC18F8X8X

N/A

FSR0H

PIC18F6X8X PIC18F8X8X

---- xxxx

---- uuuu

FSR0L

PIC18F6X8X PIC18F8X8X

xxxx xxxx

uuuu uuuu

WREG

PIC18F6X8X PIC18F8X8X

xxxx xxxx

uuuu uuuu

INDF1

PIC18F6X8X PIC18F8X8X

N/A

POSTINC1

PIC18F6X8X PIC18F8X8X

N/A

POSTDEC1

PIC18F6X8X PIC18F8X8X

N/A

PREINC1

PIC18F6X8X PIC18F8X8X

N/A

PLUSW1

PIC18F6X8X PIC18F8X8X

N/A

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1:

One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

See Table 3-2 for Reset value for specific condition.

Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

oscillator modes, they are disabled and read ‘0’.

Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’.

This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2.

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